View XC2C384-10FTG256I_5982291.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds095 (v3.2) march 8, 2007 www.xilinx.com 1 product specification ? 2002--2007 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as li sted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? optimized for 1.8v systems - as fast as 7.1 ns pin-to-pin delays - as low as 14 a quiescent current ? industry?s best 0.18 micron cmos cpld - optimized architecture for effective logic synthesis - multi-voltage i/o operation ? 1.5v to 3.3v ? available in multiple package options - 144-pin tqfp with 118 user i/o - 208-pin pqfp with 173 user i/o - 256-ball ft (1.0mm) bga with 212 user i/o - 324-ball fg (1.0mm) bga with 240 user i/o - pb-free available for all packages ? advanced system features - fastest in system programming 1.8v isp using ieee 1532 (jtag) interface - ieee1149.1 jtag boundary scan test - optional schmitt-trigger input (per pin) - unsurpassed low power management datagate enable (dge) signal control - four separate i/o banks - realdigital 100% cmos product term generation - flexible clocking modes optional dualedge triggered registers clock divider (divide by 2,4,6,8,10,12,14,16) coolclock - global signal options with macrocell control multiple global clocks with phase selection per macrocell multiple global output enables global set/reset - advanced design security - pla architecture superior pinout retention 100% product term routability across function block - open-drain output option for wired-or and led drive - optional bus-hold, 3-state or weak pullup on selected i/o pins - optional configurable grounds on unused i/os - mixed i/o voltages compatible with 1.5v, 1.8v, 2.5v, and 3.3v logic levels sstl2-1, sstl3-1, and hstl-1 i/o compatibility - hot pluggable refer to the coolrunner?-ii family data sheet for architec- ture description. description the coolrunner-ii 384-macrocell device is designed for both high performance and low power applications. this lends power savings to high-end communication equipment and high speed to battery operated devices. due to the low power stand-by and dynamic operation, overall system reli- ability is improved this device consists of twenty four function blocks inter-connected by a low power advanced interconnect matrix (aim). the aim feeds 40 true and complement inputs to each function block. the function blocks consist of a 40 by 56 p-term pla and 16 macrocells which contain numer- ous configuration bits that allow for combinational or regis- tered modes of operation. additionally, these registers can be globally reset or preset and configured as a d or t flip-flop or as a d latch. there are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. a schmitt-trigger input is available on a per input pin basis. in addition to stor- ing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins. clocking is available on a global or function block basis. three global clocks are available for all function blocks as a synchronous clock source. macrocell registers can be individually configured to power up to the zero or one state. a global set/reset control line is also available to asynchro- nously set or reset selected registers during operation. additional local clock, synchronous clock-enable, asynchro- nous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-function block basis. a dualedge flip-flop feature is also available on a per mac- rocell basis. this feature allows high performance synchro- nous operation based on lower frequency clocking to help reduce the total power consumption of the device. circuitry has also been included to divide one externally supplied global clock (gck2) by eight different selections. this yields divide by even and odd clock frequencies. the use of the clock divide (division by 2) and dualedge flip-flop gives the resultant coolclock feature. datagate is a method to selectively disable inputs of the cpld that are not of interest during certain points in time. 0 xc2c384 coolrunner-ii cpld ds095 (v3.2) march 8, 2007 00 product specification r
xc2c384 coolrunner-ii cpld 2 www.xilinx.com ds095 (v3.2) march 8, 2007 product specification r by mapping a signal to the datagate function, lower power can be achieved due to reduction in signal switching. another feature that eases voltage translation is i/o bank- ing. four i/o banks are available on the coolrunner-ii 384 macrocell device that permit easy interfacing to 3.3v, 2.5v, 1.8v, and 1.5v devices. the coolrunner-ii 384 macrocell cpld is i/o compatible with various i/o standards (see ta b l e 1 ). this device is also 1.5v i/o compatible with the use of schmitt-trigger inputs. realdigital design technology xilinx coolrunner-ii cplds are fabricated on a 0.18 micron process technology which is derived from leading edge fpga product development. coolrunner-ii cplds employ realdigital a design technique that makes use of cmos technology in both the fabrication and design methodology. realdigital design technology employs a cascade of cmos gates to implement sum of products instead of traditional sense amplifier methodology. due to this technology, xilinx coolrunner-ii cplds achieve both high-performance and low power operation. supported i/o standards the coolrunner-ii 384 macrocell features lvcmos, lvttl, sstl and hstl i/o implementations. see ta b le 1 for i/o standard voltages. the lvttl i/o standard is a gen- eral purpose eia/jedec standard for 3.3v applications that use an lvttl input buffer and push-pull output buffer. the lvcmos standard is used in 3.3v, 2.5v, 1.8v applications. both hstl and sstl i/o standards make use of a v ref pin for jedec compliance. coolrunner-ii cplds are also 1.5v i/o compatible with the use of schmitt-trigger inputs. table 1: i/o standards for xc2c384 (1) iostandard attribute output v ccio input v ccio input v ref board termination voltage v tt lvttl 3.3 3.3 n/a n/a lvcmos33 3.3 3.3 n/a n/a lvcmos25 2.5 2.5 n/a n/a lvcmos18 1.8 1.8 n/a n/a lvcmos15 (2) 1.5 1.5 n/a n/a hstl_1 1.5 1.5 0.75 0.75 sstl2_1 2.5 2.5 1.25 1.25 sstl3_1 3.3 3.3 1.5 1.5 (1)for information on assigning vref pins, see xapp399 . (2) lvcmos15 requires schmitt-trigger inputs. figure 1: i cc vs frequency table 2: i cc vs frequency (lvcmos 1.8v t a = 25c) (1) frequency (mhz) 0 25 50 75 100 125 150 175 200 typical i cc (ma) 0.023 17.5 35.03 52.53 70.03 87.53 105.03 122.35 140.03 notes: 1. 16-bit up/down, resetable binary counter (one counter per function block). frequency (mhz) ds095_01_030705 i cc (ma) 0 0 50 100 150 200 200 150 100 25 175 75 125 50
xc2c384 coolrunner-ii cpld ds095 (v3.2) march 8, 2007 www.xilinx.com 3 product specification r recommended operating conditions dc electrical characteristics (over recommended operating conditions) absolute maximum ratings (1) symbol description value units v cc supply voltage relative to ground ?0.5 to 2.0 v v ccio supply voltage for output drivers ?0.5 to 4.0 v v jtag (2) jtag input voltage limits ?0.5 to 4.0 v v ccaux jtag input supply voltage ?0.5 to 4.0 v v in (1) input voltage relative to ground ?0.5 to 4.0 v v ts (1) voltage applied to 3-state output ?0.5 to 4.0 v t stg (3) storage temperature (ambient) ?65 to +150 c t j junction temperature +150 c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easiest to achieve. during transitions, the device pins may undershoot to ?2.0v or overshoot to +4.5v, provided this over or undershoot lasts less than 10 ns and with t he forcing current being limited to 200 ma. 2. valid over commercial temperature range. 3. for soldering guidelines and thermal considerations, see the device packaging information on the xilinx website. for pb free packages, see xapp427 . symbol parameter min max units v cc supply voltage for internal logic and input buffers commercial t a = 0c to +70c 1.7 1.9 v industrial t a = ?40c to +85c 1.7 1.9 v v ccio supply voltage for output drivers @ 3.3v operation 3.0 3.6 v supply voltage for output drivers @ 2.5v operation 2.3 2.7 v supply voltage for output drivers @ 1.8v operation 1.7 1.9 v supply voltage for output drivers @ 1.5v operation 1.4 1.6 v v ccaux supply voltage for jtag programming 1.7 3.6 v symbol parameter test conditions typical max. units i ccsb standby current commercial v cc = 1.9v, v ccio = 3.6v 44 200 a i ccsb standby current industrial v cc = 1.9v, v ccio = 3.6v 79 350 a i cc (1) dynamic current f = 1 mhz 1.5 ma f = 50 mhz 45 ma c jtag jtag input capacitance f = 1 mhz - 10 pf c clk global clock input capacitance f = 1 mhz - 12 pf c io i/o capacitance f = 1 mhz - 10 pf i il (2) input leakage current v in = 0v or v ccio to 3.9v - +/?1 a i ih (2) i/o high-z leakage v in = 0v or v ccio to 3.9v - +/?1 a notes: 1. 16-bit up/down, resetable binary counter (one counter per function block). 2. see quality and reliability section of the coolrunner-ii family data sheet.
xc2c384 coolrunner-ii cpld 4 www.xilinx.com ds095 (v3.2) march 8, 2007 product specification r lvcmos and lvttl 3.3v dc voltage specifications lvcmos 2.5v dc voltage specifications (1) the v ih max value represents the jedec specification for lvcmos25. the coolrunner-ii input buffer can tolerate up to 3.9v without physical damage. lvcmos 1.8v dc voltage specifications (1) the v ih max value represents the jedec specification for lvcmos18. the coolrunner-ii input buffer can tolerate up to 3.9v without physical damage. lvcmos 1.5v dc voltage specifications (1) symbol parameter test conditions min. max. units v ccio input source voltage 3.0 3.6 v v ih high level input voltage 2 3.9 v v il low level input voltage ?0.3 0.8 v v oh high level output voltage i oh = ?8 ma, v ccio = 3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 3v - 0.4 v i ol = 0.1 ma, v ccio = 3v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 2.3 2.7 v v ih high level input voltage 1.7 v ccio + 0.3 (1) v v il low level input voltage ?0.3 0.7 v v oh high level output voltage i oh = ?8 ma, v ccio = 2.3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 2.3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 2.3v - 0.4 v i ol = 0.1 ma, v ccio = 2.3v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 1.7 1.9 v v ih high level input voltage 0.65 x v ccio v ccio + 0.3 (1) v v il low level input voltage ?0.3 0.35 x v ccio v v oh high level output voltage i oh = ?8 ma, v ccio = 1.7v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.7v v ccio ? 0.2 - v v ol low level output voltage i ol = 8 ma, v ccio = 1.7v - 0.45 v i ol = 0.1 ma, v ccio = 1.7v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 1.4 1.6 v v t+ input hysteresis threshold voltage 0.5 x v ccio 0.8 x v ccio v v t- 0.2 x v ccio 0.5 x v ccio v v oh high level output voltage i oh = ?8 ma, v ccio = 1.4v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.4v v ccio ? 0.2 - v
xc2c384 coolrunner-ii cpld ds095 (v3.2) march 8, 2007 www.xilinx.com 5 product specification r schmitt trigger input dc voltage specifications sstl2-1 dc voltage specifications sstl3-1 dc voltage specifications hstl1 dc voltage specifications v ol low level output voltage i ol = 8 ma, v ccio = 1.4v - 0.4 v i ol = 0.1 ma, v ccio = 1.4v - 0.2 v notes: 1. hysteresis used on 1.5v inputs. symbol parameter test conditions min. max. units v ccio input source voltage 1.4 3.9 v v t+ input hysteresis threshold voltage 0.5 x v ccio 0.8 x v ccio v v t- 0.2 x v ccio 0.5 x v ccio v symbol parameter test conditions min. typ max. units v ccio input source voltage - 2.3 2.5 2.7 v v ref(1) input reference voltage - 1.15 1.25 1.35 v v tt(2) termination voltage - v ref ? 0.04 1.25 v ref + 0.04 v v ih high level input voltage - v ref + 0.18 - 3.9 v v il low level input voltage - ?0.3 - v ref ? 0.18 v v oh high level output voltage i oh = ?8 ma, v ccio = 2.3v v ccio ? 0.62 - - v v ol low level output voltage i ol = 8 ma, v ccio = 2.3v - - 0.54 v notes: 1. v ref should track the variations in v ccio , also peak to peak ac noise on v ref may not exceed 2% v ref. 2. v tt of transmitting device must track v ref of receiving devices. symbol parameter test conditions min. typ max. units v ccio input source voltage - 3.0 3.3 3.6 v v ref(1) input reference voltage - 1.3 1.5 1.7 v v tt(2) termination voltage - v ref ? 0.05 1.5 v ref + 0.05 v v ih high level input voltage - v ref + 0.2 - v ccio + 0.3 v v il low level input voltage - ?0.3 - v ref ? 0.2 v v oh high level output voltage i oh = ?8 ma, v ccio = 3v v ccio ? 1.1 - - v v ol low level output voltage i ol = 8 ma, v ccio = 3v - - 0.7 v notes: 1. v ref should track the variations in v ccio , also peak to peak ac noise on v ref may not exceed 2% v ref. 2. v tt of transmitting device must track v ref of receiving devices. symbol parameter test conditions min. typ max. units v ccio input source voltage 1.4 1.5 1.6 v v ref(1) input reference voltage 0.68 0.75 0.90 v v tt(2) termination voltage - v ccio * 0.5 - v v ih high level input voltage v ref + 0.1 - 1.9 v symbol parameter test conditions min. max. units
xc2c384 coolrunner-ii cpld 6 www.xilinx.com ds095 (v3.2) march 8, 2007 product specification r v il low level input voltage ?0.3 - v ref ? 0.1 v v oh high level output voltage i oh = ?8 ma, v ccio = 1.4v v ccio ? 0.4 - - v v ol low level output voltage i ol = 8 ma, v ccio = 1.4v - - 0.4 v symbol parameter test conditions min. typ max. units
xc2c384 coolrunner-ii cpld ds095 (v3.2) march 8, 2007 www.xilinx.com 7 product specification r ac electrical characteristics over recommended operating conditions symbol parameter -7 -10 units min. max. min. max. t pd1 propagation delay single p-term - 7.1 - 9.2 ns t pd2 propagation delay or array - 7.5 - 10.0 ns t sud direct input register set-up time 4.1 - 4.2 - ns t su1 setup time fast (single p-term) 3.2 - 3.3 - ns t su2 setup time (or array) 3.6 - 4.1 - ns t hd direct input register hold time 0.0 - 0.0 - ns t h hold time (or array or p-term) 0.0 - 0.0 - ns t co clock to output - 5.3 - 7.9 ns f toggle (1) internal toggle rate - 350 - 166 mhz f system1 (2) maximum system frequency - 217 - 125 mhz f system2 (2) maximum system frequency - 200 - 114 mhz f ext1 (3) maximum external frequency - 118 - 89 mhz f ext2 (3) maximum external frequency - 112 - 83 mhz t psud direct input register p-term clock setup time 2.3 - 2.5 - ns t psu1 p-term clock setup time (single p-term) 1.4 - 1.9 - ns t psu2 p-term clock setup time (or array) 1.8 - 2.7 - ns t phd direct input register p-term clock hold time 0.9 - 0.4 - ns t ph p-term clock hold 1.8 - 1.3 - ns t pco p-term clock to output - 7.1 - 9.3 ns t oe /t od global oe to output enable/disable - 6.0 - 9.2 ns t poe /t pod p-term oe to output enable/disable - 7.0 - 10.2 ns t moe /t mod macrocell driven oe to output enable/disable - 8.0 - 12.5 ns t pao p-term set/reset to output valid - 7.5 - 11.6 ns t ao global set/reset to output valid - 6.0 - 11.5 ns t suec register clock enable setup time 3.3 - 3.4 - ns t hec register clock enable hold time 0.0 - 0.0 - ns t cw global clock pulse width high or low 1.4 - 3.0 - ns t pcw p-term pulse width high or low 7.5 - 10.0 - ns t aprpw asynchronous preset/reset pulse width (high or low) 7.5 - 10.0 - ns t dgsu set-up before datagate latch assertion 0.0 0.0 ns t dgh hold to datagate latch assertion 4.0 6.0 ns t dgr datagate recovery to new data 8.5 11.0 ns t dgw datagate low pulse width 3.0 5.0 ns t cdrsu cdrst setup time before falling edge gclk2 1.7 2.5 ns t cdrh cdrst hold time before falling edge gclk2 0.0 0.0 ns t config configuration time 200 200 s notes: 1. f toggle is the maximum frequency of a t flip-flop can reliably toggle (see coolrunner-ii family data sheet). 2. f system1 (1/t cycle ) is the internal operating frequency for a device with 16-bit resetable binary counter through one p-term per macrocell while f system2 is through the or array (one counter per function block) 3. f ext1 (1/t su1 +t co ) is the maximum external frequency using one p-term while f ext2 is through the or array 4. typical configuration current during t config is 25 ma.
xc2c384 coolrunner-ii cpld 8 www.xilinx.com ds095 (v3.2) march 8, 2007 product specification r internal timing parameters symbol parameter (1) -7 -10 units min. max. min. max. buffer delays t in input buffer delay - 3.1 - 3.8 ns t din direct data register input delay - 4.5 - 5.5 ns t gck global clock buffer delay - 2.1 - 3.3 ns t gsr global set/reset buffer delay - 2.4 - 4.6 ns t gts global 3-state buffer delay - 2.9 - 3.7 ns t out output buffer delay - 3.0 - 3.9 ns t en output buffer enable/disable delay - 3.1 - 5.5 ns p-term delays t ct control term delay - 0.8 - 0.9 ns t logi1 single p-term delay adder - 0.5 - 0.8 ns t logi2 multiple p-term delay adder - 0.4 - 0.8 ns macrocell delay t pdi input to output valid - 0.5 - 0.7 ns t sui setup before clock 1.7 - 2.0 - ns t hi hold after clock 0.0 - 0.0 - ns t ecsu enable clock setup time 1.5 - 2.0 - ns t echo enable clock hold time 0.0 - 0.0 - ns t coi clock to output valid - 0.2 - 0.7 ns t aoi set/reset to output valid - 0.6 - 3.0 ns t cdbl clock doubler delay - 0 - 0 ns feedback delays t f feedback delay - 2.2 - 4.5 ns t oem macrocell to global oe delay - 2.6 - 3.0 ns i/o standard time adder delays 1.5v cmos t hys15 hysteresis input adder - 3.0 - 4.0 ns t out15 output adder - 0.8 - 1.0 ns t slew15 output slew rate adder - 4.0 - 4.0 ns i/o standard time adder delays 1.8v cmos t hys18 hysteresis input adder - 2.0 - 4.0 ns t out18 output adder - 0.0 - 0.0 ns t slew output slew rate adder - 2.0 - 4.0 ns i/o standard time adder delays 2.5v cmos t in25 standard input adder - 0.6 - 1.0 ns t hys25 hysteresis input adder - 1.5 - 3.0 ns t out25 output adder - 0.8 - 3.0 ns t slew25 output slew rate adder - 3.0 - 4.0 ns
xc2c384 coolrunner-ii cpld ds095 (v3.2) march 8, 2007 www.xilinx.com 9 product specification r switching characteristics switching test conditions i/o standard time adder delays 3.3v cmos/ttl t in33 standard input adder - 0.5 - 2.0 ns t hys33 hysteresis input adder - 1.2 - 3.0 ns t out33 output adder - 1.2 - 3.0 ns t slew33 output slew rate adder - 3.0 - 4.0 ns i/o standard time adder delays hstl, sstl sstl2-1 input adder to t in , t din , t gck , t gsr , t gts - 0.8 - 2.5 ns output adder to t out - -0.5 - 0.0 ns sstl3-1 input adder to t in , t din , t gck , t gsr , t gts - 0.8 - 2.5 ns output adder to t out - -0.50 - 0.00 ns hstl-1 input adder to t in , t din , t gck , t gsr , t gts - 1.0 - 2.5 ns output adder to t out - 0.0 - 0.0 ns notes: 1. 1.5 ns input pin signal rise/fall. internal timing parameters (continued) symbol parameter (1) -7 -10 units min. max. min. max. figure 2: derating curve for t pd number of outputs switching 12 4 8 16 4.0 5.0 6.0 v cc = v ccio = 1.8v, 25 o c t pd2 (ns) 5.5 4.5 ds095_02_053103 figure 3: ac load circuit r 1 v cc c l r 2 device under test output type lvttl33 lvcmos33 lvcmos25 lvcmos18 lvcmos15 r 1 268 275 188 112.5 150 r 2 235 275 188 112.5 150 c l 35 pf 35 pf 35 pf 35 pf 35 pf ds092_03_09230 2 test point notes: 1. c l includes test fixtures and probe capacitance. 2. 1.5 nsec maximum rise/fall times on inputs.
xc2c384 coolrunner-ii cpld 10 www.xilinx.com ds095 (v3.2) march 8, 2007 product specification r typical i/v output curves the i/v curve illustrates the nominal amount of current that an i/o can source/sink at different voltage levels. 11 figure 4: typical i/v curves for xc2c384 vo (output volts) xc384_iv_05070 3 io (output current ma) 0 0 40 10 50 20 30 60 3.0 2.5 2.0 1.5 1.0 .5 3 .5 3.3v 1.5v 1.8v 2.5v iol pin descriptions function block macro- cell tq144 pq208 ft256 fg324 i/o bank 11-2b3c32 1 2 - 208 b4 a1 2 1(gsr) 3 143 206 c4 a2 2 1 4 142 205 a2 b3 2 15---c42 16----- 17----- 18----- 19----- 110----- 111----- 1 12 140 203 c5 b4 2 1 13 139 202 a3 c5 2 1 14 - 201 - b5 2 1 15 - 200 e7 a3 2 1 16 - 199 - a4 2 2(gts2) 1 2 3 d3 d3 2 22-4c3b22 2(gts3) 3 3 5 e3 b1 2 2446b2c22 2(gts0) 5 5 7 d4 c1 2 26----- 27----- 28----- 29----- 210----- 211----- 212--a1d22 2 13- 8d2f4 2 214--c2e22 2(gts1) 15 6 9 e5 e1 2 216710b1f22 pin descriptions (continued) function block macro- cell tq144 pq208 ft256 fg324 i/o bank
xc2c384 coolrunner-ii cpld ds095 (v3.2) march 8, 2007 www.xilinx.com 11 product specification r 3 1 - 198 a4 d6 2 3 2 - 197 - a5 2 3 3 138 196 c6 c6 2 3 4 137 195 b5 b6 2 3 5 136 194 d6 a6 2 36----- 37----- 38----- 39----- 310----- 311----- 3 12 135 193 a5 d7 2 3 13 - 192 e8 c7 2 314--b6b72 3 15 - 191 c7 a7 2 316134-a6d82 41912e4g42 4210-c1g32 431114e2g22 4 4 12 15 f2 g1 2 45-16e6h42 46----- 47----- 48----- 49----- 410----- 411----- 412-17f3h32 4 13 - 18 d1 h2 2 414-19g4h12 415-20e1j32 416-21g3j22 pin descriptions (continued) function block macro- cell tq144 pq208 ft256 fg324 i/o bank 5 1 - - d7 c8 2 5 2 133 - b7 b8 2 5 3 132 - e9 a8 2 54-189a7d92 5 5 - 188 d8 c9 2 56----- 57----- 58----- 59----- 510----- 511----- 512-187b8b92 513131186c8a92 514-185a8d102 515130184e11c102 5 16 129 183 e10 b10 2 61-22g2j12 6 2 13 - f5 k3 2 631423f1k22 6415-g5k12 65--h2l12 66----- 67----- 68----- 69----- 610----- 611----- 612--h4l32 61316-g1l22 61417-h3m12 615--h1m22 6161825h5m32 pin descriptions (continued) function block macro- cell tq144 pq208 ft256 fg324 i/o bank
xc2c384 coolrunner-ii cpld 12 www.xilinx.com ds095 (v3.2) march 8, 2007 product specification r 7(cdrst) 1 35 51 p2 ab2 1 7 2 - 50 n3 aa2 1 7 3 - 49 r1 aa1 1 7 4 34 48 n4 w4 1 7 5 33 47 n2 y2 1 76----- 77----- 78----- 79----- 710----- 711----- 7(gck1)123246m3y1 1 713--p1w21 7143145m4w11 7(gck0)153044m2v3 1 7 16 - 43 l3 u4 1 81-54p4y41 8(gck2) 2 38 55 p5 ab3 1 8 3 - 56 r2 aa4 1 84-57t1y51 8(dge) 5 39 58 t2 aa5 1 86----- 87----- 88----- 89----- 810----- 811----- 8 12 - - - ab4 1 8134060n5w61 8 14 41 - - ab5 1 8154261r4y61 8 16 43 - m5 aa6 1 pin descriptions (continued) function block macro- cell tq144 pq208 ft256 fg324 i/o bank 9 1 - 41n1v2 1 9 2 28 40 l4 v1 1 93-39m1u31 94-38l5u21 95-37k4u11 96----- 97----- 98----- 99----- 910----- 911------ 9 12 - 36 l2 t4 1 913-35k3t31 9 14 - 34 l1 t2 1 9152632-t11 9 1625- -r41 10 1 44 62 - ab6 1 10 2 45 63 r5 w7 1 10 3 - - - y7 1 10 4 46 64 r6 aa7 1 10 5 - 65 n6 ab7 1 10 6 - - - - - 10 7 - - - - - 10 8 - - - - - 10 9 - - - - - 10 10 - - - - - 10 11 - - - - - 10 12 - 66 r3 w8 1 10 13 - 67m6y8 1 10 14 48 69 - aa8 1 10 15 49 70 t3 ab8 1 10 16 50 71 p6 y9 1 pin descriptions (continued) function block macro- cell tq144 pq208 ft256 fg324 i/o bank
xc2c384 coolrunner-ii cpld ds095 (v3.2) march 8, 2007 www.xilinx.com 13 product specification r 11 1 24 31 k5 r3 1 11 2 23 - k2 r2 1 11 3 22 30 j4 r1 1 11 4 21 29 k1 p4 1 11 5 20 28 j3 p3 1 11 6 - - - - - 11 7 - - - - - 11 8 - - - - - 11 9 - - - - - 11 10 - - - - - 11 11 - - - - - 11 12 19 27 j2 p2 1 11 13 - - j5 p1 1 11 14 - - j1 n3 1 11 15 - - - n2 1 11 16 - - - n1 1 12 1 51 72 t4 aa9 1 12 2 52 73 p7 ab9 1 12 3 53 74 t5 w10 1 12 4 - 75 n7 y10 1 12 5 54 76 r7 aa10 1 12 6 - - - - - 12 7 - - - - - 12 8 - - - - - 12 9 - - - - - 12 10 - - - - - 12 11 - - - - - 12 12 - 77 m7 ab10 1 12 13 - - - ab11 1 12 14 - - - w11 1 12 15 - - - aa11 1 12 16 - 78 t6 y11 1 pin descriptions (continued) function block macro- cell tq144 pq208 ft256 fg324 i/o bank 13 1 - - b16 c21 4 13 2 - - g11 c20 4 13 3 112 160 c14 b22 4 13 4 113 161 b15 b21 4 13 5 - - a16 a22 4 13 6 - - - - - 13 7 - - - - - 13 8 - - - - - 13 9 - - - - - 13 10 - - - - - 13 11 - - - - - 13 12 114 162 b13 a21 4 13 13 115 163 b14 b20 4 13 14 - - c13 c19 4 13 15 - - a15 b19 4 13 16 - 164 c12 c18 4 14 1 111 159 d14 d19 4 14 2 110 158 c15 d20 4 14 3 107 155 g12 c22 4 14 4 106 154 d15 d21 4 14 5 105 153 e14 d22 4 14 6 - - - - - 14 7 - - - - - 14 8 - - - - - 14 9 - - - - - 14 10 - - - - - 14 11 - - - - - 14 12 - - c16 e20 4 14 13 104 152 f14 f19 4 14 14 - 151 d16 e21 4 14 15 - - f13 e22 4 14 16 - 150 e15 f20 4 pin descriptions (continued) function block macro- cell tq144 pq208 ft256 fg324 i/o bank
xc2c384 coolrunner-ii cpld 14 www.xilinx.com ds095 (v3.2) march 8, 2007 product specification r 15 1 - - b12 b18 4 15 2 116 165 d13 a19 4 15 3 - 166 a14 d17 4 15 4 - - e13 a18 4 15 5 117 167 a13 c17 4 15 6 - - - - - 15 7 - - - - - 15 8 - - - - - 15 9 - - - - - 15 10 - - - - - 15 11 - - - - - 15 12 - 168 c11 b17 4 15 13 118 169 a12 d16 4 15 14 - - b11 c16 4 15 15 119 170 d11 b16 4 15 16 120 171 a11 d15 4 16 1 103 149 g13 f21 4 16 2 - 148 f15 f22 4 16 3 102 147 g14 g19 4 16 4 - 146 e16 g20 4 16 5 - - h12 g21 4 16 6 - - - - - 16 7 - - - - - 16 8 - - - - - 16 9 - - - - - 16 10 - - - - - 16 11 - - - - - 16 12 - 145 f16 g22 4 16 13 - - h16 h19 4 16 14 101 144 - h21 4 16 15 - - - h22 4 16 16 100 143 - j19 4 pin descriptions (continued) function block macro- cell tq144 pq208 ft256 fg324 i/o bank 17 1 - 173 d10 c15 4 17 2 121 174 b10 b15 4 17 3 - 175 e12 d14 4 17 4 - - - b14 4 17 5 - - f12 c13 4 17 6 - - - - - 17 7 - - - - - 17 8 - - - - - 17 9 - - - - - 17 10 - - - - - 17 11 - - - - - 17 12 124 178 b9 a13 4 17 13 125 179 c9 d12 4 17 14 126 180 c10 c12 4 17 15 - - a9 b11 4 17 16 128 182 d9 a10 4 18 1 - - g15 j20 4 18 2 - 142 - j21 4 18 3 98 140 - j22 4 18 4 97 139 h13 k19 4 18 5 96 138 g16 k20 4 18 6 - - - - - 18 7 - - - - - 18 8 - - - - - 18 9 - - - - - 18 10 - - - - - 18 11 - - - - - 18 12 95 137 h14 k21 4 18 13 94 136 h15 k22 4 18 14 - 135 j12 l19 4 18 15 - 134 k12 l20 4 18 16 - - j16 l21 4 pin descriptions (continued) function block macro- cell tq144 pq208 ft256 fg324 i/o bank
xc2c384 coolrunner-ii cpld ds095 (v3.2) march 8, 2007 www.xilinx.com 15 product specification r 19 1 - 103 p13 aa22 3 19 2 - - p14 y20 3 19 3 74 106 p15 y21 3 19 4 75 107 r15 w20 3 19 5 76 108 t16 w21 3 19 6 - - - - - 19 7 - - - - - 19 8 - - - - - 19 9 - - - - - 19 10 - - - - - 19 11 - - - - - 19 12 77 109 n14 y22 3 19 13 78 110 r16 w22 3 19 14 79 111 n15 v20 3 19 15 - 112 m15 v21 3 19 16 - 113 m13 u19 3 20 1 71 102 r13 ab22 3 20 2 70 101 n13 aa21 3 20 3 69 100 r14 ab21 3 20 4 68 99 t15 w19 3 20 5 66 97 r12 aa20 3 20 6 - - - - - 20 7 - - - - - 20 8 - - - - - 20 9 - - - - - 20 10 - - - - - 20 11 - - - - - 20 12 - - t14 y18 3 20 13 64 95 n11 aa19 3 20 14 - - p11 y17 3 20 15 - - m11 aa18 3 20 16 - - t13 ab18 3 pin descriptions (continued) function block macro- cell tq144 pq208 ft256 fg324 i/o bank 21 1 80 114 p16 v22 3 21 2 - 115 n16 u20 3 21 3 81 116 l14 u21 3 21 4 - 117 m14 u22 3 21 5 - 118 l15 t19 3 21 6 - - - - - 21 7 - - - - - 21 8 - - - - - 21 9 - - - - - 21 10 - - - - - 21 11 - - - - - 21 12 82 119 l13 t20 3 21 13 - 120 m12 t21 3 21 14 - 121 m16 t22 3 21 15 83 122 k14 r21 3 21 16 - 123 - r22 3 22 1 - - n10 aa17 3 22 2 61 91 t12 ab17 3 22 3 - 90 p10 y16 3 22 4 - 89 t11 aa16 3 22 5 - - r10 ab16 3 22 6 - - - - - 22 7 - - - - - 22 8 - - - - - 22 9 - - - - - 22 10 - - - - - 22 11 - - - - - 22 12 60 88 m10 w15 3 22 13 - 87 t10 y15 3 22 14 59 86 m9 aa15 3 22 15 - 85 r9 ab15 3 22 16 - - p9 w14 3 pin descriptions (continued) function block macro- cell tq144 pq208 ft256 fg324 i/o bank
xc2c384 coolrunner-ii cpld 16 www.xilinx.com ds095 (v3.2) march 8, 2007 product specification r 23 1 - - l16 p20 3 23 2 - 125 k15 p21 3 23 3 85 126 l12 n19 3 23 4 86 127 - n21 3 23 5 87 - k16 n22 3 23 6 - - - - - 23 7 - - - - - 23 8 - - - - - 23 9 - - - - - 23 10 - - - - - 23 11 - - - - - 23 12 88 128 j14 m22 3 23 13 91 - j15 m19 3 23 14 92 131 j13 m20 3 23 15 - - - m21 3 23 16 - - - l22 3 pin descriptions (continued) function block macro- cell tq144 pq208 ft256 fg324 i/o bank 24 1 - - n9 y14 3 24 2 58 84 t9 aa14 3 24 3 - - - ab14 3 24 4 - 83 - y13 3 24 5 - 82 m8 aa13 3 24 6 - - - - - 24 7 - - - - - 24 8 - - - - - 24 9 - - - - - 24 10 - - - - - 24 11 - - - - - 24 12 57 - t8 ab13 3 24 13 - - p8 w12 3 24 14 56 80 r8 y12 3 24 15 - - t7 aa12 3 24 16 - - n8 ab12 3 notes: 1. gts = global output enable, gsr = global reset/set, gck = global clock, cdrst = clock divide reset, dge = datagate enable. 2. gck, gsr, and gts pins can also be used for general purpose i/o. pin descriptions (continued) function block macro- cell tq144 pq208 ft256 fg324 i/o bank xc2c384 jtag, power/ground, no connect pins and total user i/o pin type tq144 pq208 ft256 fg324 tck 67 98 p12 y19 tdi 63 94 r11 ab19 tdo 122 176 a10 c14 tms 65 96 n12 ab20 v ccaux (jtag supply voltage) 811 f4 f1 power internal (v cc ) 1, 37, 84 1, 53, 124 p3, k13, d12, d5 aa3, n20, a20, d4, e3 power bank 1 i/o (v ccio1 ) 27, 55 33, 59, 79 j6, k6, l7, l8 m9, n9, p10, p11 power bank 2 i/o (v ccio2 ) 141 26, 204 f7, f8, g6, h6 j10, j11, k9, l9 power bank 3 i/o (v ccio3 ) 73, 93 92, 105, 132 j11, k11, l10, l9 m14, n14, p12, p13 power bank 4 i/o (v ccio4 ) 109, 127 133, 157, 172, 181 f10, f9, h11 j12, j13, k14, l14
xc2c384 coolrunner-ii cpld ds095 (v3.2) march 8, 2007 www.xilinx.com 17 product specification r ground 29, 36, 47, 62, 72, 89, 90, 99, 108, 123, 144 13, 24, 42, 52, 68, 81, 93, 104, 129, 130, 141, 156, 177, 190, 207 f11, f6, g10, g7, g8, g9, h10, h7, h8, h9, j10, j7, j8, j9, k10, k7, k8, k9, l11, l6 d5, d18, e4, e19, j9, j14, k10, k11, k12, k13, l10, l11, l12, l13, m10, m11, m12, m13, n10, n11, n12, n13, p9, p14, v4, v19, w5, w18 no connects - - a11,a12,a14,a15,a16,a17,b 12,b13,c11,d1,d11,d13,f3,h 20,j4,k4,l4,m4,n4,p19,p22, r19,r20,w3,w9,w13,w16,w 17,y3,ab1 total user i/o (includes dual function pins) 118 173 212 240 xc2c384 jtag, power/ground, no connect pins and total user i/o (continued) pin type tq144 pq208 ft256 fg324
xc2c384 coolrunner-ii cpld 18 www.xilinx.com ds095 (v3.2) march 8, 2007 product specification r ordering information part number pin/ball spacing ja (c/watt) jc (c/watt) package type package body dimensions i/o comm. (c) ind. (i) (1) xc2c384-7tq144c 0.5mm 34.1 6.5 thin quad flat pack 20mm x 20mm 118 c xc2c384-10tq144c 0.5mm 34.1 6.5 thin quad flat pack 20mm x 20mm 118 c xc2c384-7pq208c 0.5mm 36.1 8.4 plastic quad flat pack 28mm x 28mm 173 c xc2c384-10pq208c 0.5mm 36.1 8.4 plastic quad flat pack 28mm x 28mm 173 c xc2c384-7ft256c 1.0mm 33.5 5.5 fine pitch thin bga 17mm x 17mm 212 c xc2c384-10ft256c 1.0mm 33.5 5.5 fine pitch thin bga 17mm x 17mm 212 c xc2c384-7fg324c 1.0mm 39.3 5.3 fine pitch bga 23mm x 23mm 240 c xc2c384-10fg324c 1.0mm 39.3 5.3 fine pitch bga 23mm x 23mm 240 c xc2c384-7tqg144c 0.5mm 34.1 6.5 thin quad flat pack; pb-free 20mm x 20mm 118 c xc2c384-10tqg144c 0.5mm 34.1 6.5 thin quad flat pack; pb-free 20mm x 20mm 118 c xc2c384-7pqg208c 0.5mm 36.1 8.4 plastic quad flat pack; pb-free 28mm x 28mm 173 c xc2c384-10pqg208c 0.5mm 36.1 8.4 plastic quad flat pack; pb-free 28mm x 28mm 173 c xc2c384-7ftg256c 1.0mm 33.5 5.5 fine pitch thin bga; pb-free 17mm x 17mm 212 c xc2c384-10ftg256c 1.0mm 33.5 5.5 fine pitch thin bga; pb-free 17mm x 17mm 212 c xc2c384-7fgg324c 1.0mm 39.3 5.3 fine pitch bga; pb-free 23mm x 23mm 240 c xc2c384-10fgg324c 1.0mm 39.3 5.3 fine pitch bga; pb-free 23mm x 23mm 240 c xc2c384-10tq144i 0.5mm 34.1 6.5 plastic quad flat pack 20mm x 20mm 118 i xc2c384-10pq208i 0.5mm 36.1 8.4 plastic quad flat pack 28mm x 28mm 173 i xc2c384-10ft256i 1.0mm 33.5 5.5 fine pitch thin bga 17mm x 17mm 212 i xc2c384-10fg324i 1.0mm 39.3 5.3 fine pitch bga 23mm x 23mm 240 i xc2c384-10tqg144i 0.5mm 34.1 6.5 plastic quad flat pack; pb-free 20mm x 20mm 118 i xc2c384-10pqg208i 0.5mm 36.1 8.4 plastic quad flat pack; pb-free 28mm x 28mm 173 i XC2C384-10FTG256I 1.0mm 33.5 5.5 fine pitch thin bga; pb-free 17mm x 17mm 212 i xc2c384-10fgg324i 1.0mm 39.3 5.3 fine pitch bga; pb-free 23mm x 23mm 240 i notes: 1. c = commercial (t a = 0c to +70c); i = industrial (t a = ?40c to +85c).. standard example: xc2c128 device speed grade package type number of pins temperature range -7 tq c 144 pb- free example: xc2c128 tq g 144 c device speed grade package type pb -free number of pins -7 temperature range
xc2c384 coolrunner-ii cpld ds095 (v3.2) march 8, 2007 www.xilinx.com 19 product specification r device part marking figure 5: sample package with part marking xc2cxxx tq144 7c device type package speed operating range this line not related to device part number part marking for non-chip scale package r
xc2c384 coolrunner-ii cpld 20 www.xilinx.com ds095 (v3.2) march 8, 2007 product specification r figure 6: tq144 thin quad flat pack v cc i/o (1) i/o (1) i/o i/o (1) i/o (1) i/o v aux i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio1 i/o gnd i/o (2) i/o i/o (2) i/o i/o i/o (4) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 tq144 top view v cc i/o (2) i/o (5) i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o v ccio1 i/o i/o i/o i/o i/o i/o gnd tdi i/o tms i/o tck i/o i/o i/o i/o gnd 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 gnd i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o v ccio3 i/o i/o gnd gnd i/o i/o i/o i/o v cc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio3 gnd i/o (3) i/o v ccio2 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio4 i/o i/o i/o gnd tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio4 (1) - global output enable (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - datagate enable
xc2c384 coolrunner-ii cpld ds095 (v3.2) march 8, 2007 www.xilinx.com 21 product specification r figure 7: pq208 plastic quad flat package vcc i/o i/o(1) i/o i/o(1) i/o i/o(1) i/o i/o(1) i/o vaux i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o vccio2 i/o i/o i/o i/o i/o i/o vccio1 i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o(2) i/o i/o(2) i/o i/o i/o i/o i/o(4) gnd pq208 top view vcc i/o i/o(2) i/o i/o i/o(5) vccio1 i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio1 i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio3 gnd tdi i/o tms i/o tck i/o i/o i/o i/o i/o gnd (1) - global output enable (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - datagate enable gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o vccio4 vccio3 i/o gnd gnd i/o i/o i/o i/o vcc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio3 i/o gnd i/o(3) i/o vccio2 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o vccio4 i/o i/o i/o gnd tdo i/o i/o i/o vccio4 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
xc2c384 coolrunner-ii cpld 22 www.xilinx.com ds095 (v3.2) march 8, 2007 product specification r figure 8: ft256 fine pitch thin bga ft256 bottom view a b c d e f g h j k l m n p r t 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 i/o tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(3) i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(1) i/o i/o vcc i/o i/o i/o i/o i/o vcc i/o(1) i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(1) i/o(1) i/o i/o i/o i/o vccio4 vaux i/o i/o i/o gnd vccio4 vccio2 vccio2 gnd i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o gnd gnd gnd vccio2 i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o vccio4 gnd gnd gnd vccio2 i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o vccio3 gnd gnd gnd vccio1 i/o i/o i/o i/o i/o i/o gnd i/o vcc i/o i/o vccio3 gnd gnd gnd vccio1 i/o i/o i/o i/o i/o i/o vccio3 i/o i/o i/o i/o gnd vccio3 vccio1 vccio1 gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(2) i/o(2) i/o i/o i/o i/o i/o i/o i/o tms i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o tck i/o i/o i/o i/o i/o i/o(2) vcc i/o(4) i/o i/o i/o i/o i/o i/o i/o i/o tdi i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(5) i/o i/o (1) - global output enable (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - datagate enable
xc2c384 coolrunner-ii cpld ds095 (v3.2) march 8, 2007 www.xilinx.com 23 product specification r figure 9: fg324 fine pitch bga fg324 bottom view a b c d e f g h j k l m n p r t u v w y aa ab 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 i/o nc i/o i/o vcc i/o nc nc nc i/o nc nc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o nc nc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o tdo i/o i/o nc i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o nc i/o nc i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o nc i/o i/o vccio2 i/o i/o gnd vccio4 vccio4 vccio2 gnd i/o i/o gnd i/o i/o vccio4 gnd gnd gnd vccio2 i/o i/o gnd i/o i/o vccio4 gnd gnd gnd vccio2 i/o i/o gnd i/o i/o vccio3 gnd gnd gnd vccio1 i/o i/o gnd i/o vcc vccio3 gnd gnd gnd vccio1 i/o nc vccio1 nc i/o gnd vccio3 vccio3 vccio1 gnd i/o i/o nc nc i/o i/o i/o i/o i/o (1) - global output enable (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - datagate enable gnd vcc i/o i/o(1) i/o nc i/o vaux i/o i/o i/o i/o i/o i/o i/o i/o nc i/o i/o i/o nc i/o i/o i/o nc i/o i/o i/o nc i/o i/o i/o nc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o gnd i/o(2) i/o i/o i/o nc i/o i/o i/o gnd nc i/o i/o nc i/o i/o nc i/o i/o i/o i/o i/o gnd nc i/o i/o i/o i/o i/o tck i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o nc i/o i/o(2) i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(5) vcc i/o i/o i/o i/o i/o tdi tms i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(2) i/o(4) nc vcc i/o gnd i/o(1) i/o nc i/o i/o i/o i/o i/o i/o(1) i/o i/o i/o i/o i/o i/o(1) i/o i/o i/o i/o i/o(3) i/o
xc2c384 coolrunner-ii cpld 24 www.xilinx.com ds095 (v3.2) march 8, 2007 product specification r warranty disclaimer these products are subject to the terms of the xilinx limited warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of the products in an application or environment that is not within the specifications stated on the then-current xilinx data sheet for the produc ts. products are not designed to be fail-safe and are not warranted for use in applications th at pose a risk of physical harm or loss of life. use of products in such applications is fully at the risk of customer subject to applicable laws and regulations. additional information additional information is available for the following coolrunner-ii topics: ? xapp784: bulletproof cpld design practices ? xapp375: timing model ? xapp376: logic engine ? xapp378: advanced features ? xapp382: i/o characteristics ? xapp389: powering coolrunner-ii ? xapp399: assigning vref pins to access these and all application notes with their associ- ated reference designs, click the following link and scroll down the page until you find the document you want: coolrunner-ii data sheets and application notes device packages revision history the following table shows the revision history for this document. date version revision 5/31/02 1.0 initial xilinx release 9/23/02 1.1 updated ft256 and tq144 pinouts 4/16/03 1.2 updated fg324 package, updated no connect pins 5/30/03 2.0 added -6, -10 characterization data 11/7/03 2.1 corrected typo on page 1. 324-ball fg bga package has ball pitch of 1.0mm 1/26/04 2.2 added links to application notes and data sheets 5/7/04 2.3 corrected error in package dimensions of xc2c384-10tq144i 8/03/04 2.4 pb-free documentation 10/01/04 2.5 add asynchronous preset/reset pulse width specification to ac electrical characteristics 01/30/05 2.6 change to i ccsb max for industrial devices 03/07/05 2.7 deleted -6 speed grade. modifications to table 1, iostandards 2/06/06 2.8 change to t sui for -7 speed grade. previous value was typographical error 03/20/06 2.9 add warranty disclaimer. add note to pin descriptions that gck, gsr, and gts pins can also be used for general purpose i/o
xc2c384 coolrunner-ii cpld ds095 (v3.2) march 8, 2007 www.xilinx.com 25 product specification r 07/14/06 3.0 move to product specification. changes to - 7 speed grade: t sud , t su1 , t su2 , t co , t pco , t f , f ext1 , t gck , t ecsu , t coi , t suec , t cw and f ext2 . changes to -10 speed grade: t sud , t su1 , t su2 , t psud , f system1 , f system2 , f ext , and f ext2. change to test conditions for v oh and v ol on hstl1 dc voltage specifications, page 5 (v ccio goes to 1.4v from 1.7v). 02/15/07 3.1 corrections to timing parameters t oem for -6 speed grade, and to t din , t sui , t ecsu , t psu1 , t psu2 , t phd ,and t suec for the -7 speed grade. values now match the software. there were no changes to silicon or characterization. change to v ih specification for 2.5v and 1.8v lvcmos. 03/08/07 3.2 fixed typo in note for v il for lvcmos18; removed note for v il for lvcmos33. date version revision
xc2c384 coolrunner-ii cpld 26 www.xilinx.com ds095 (v3.2) march 8, 2007 product specification r

▲Up To Search▲

Price & Availability of XC2C384-10FTG256I

	To Download XC2C384-10FTG256I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .